During the manufacturing of monocrystalline Silicon ingot for wafer production, interstitial and vacancy defects are formed in the crystal lattice. Presence of these defects in wafers have major impact on the performance of Silicon based electronic devices. A single vacancy or interstitial defect does not have any detrimental effect on the working of the device, but practically in the wafer these defects exists as agglomerates or aggregates. Agglomeration of vacancies results in the formation of tiny holes on the surface, of size ranging from 50-150 nm. These holes are also known as Light point defects (LPD) and are common in Silicon grown by Czochralski (CZ) method. These defects were the major cause of breakdown of gate oxide in memory devices in year 1980. Another defect that is commonly found in Silicon grown by Floating zone (FZ) method is network of dislocation loops ,few micron in size, formed due to aggregation of interstitial defects. These defects are also known as Crystal originated particles (COP). As the size of electronic device is reducing, detrimental effect of COP on device performance is getting significant. Since the beginning, focus of Si based semiconductor industries is to reduce these defects and it has now been possible to simulate the behavior of the defect formation which has made possible for industries to tailor them as per requirement of device manufacturers.
As a researcher or manufacturer working on device fabrication, it is always important to take LPD and COP into consideration. It is practically impossible to have completely defect free Si wafer. But these defects can now be minimized or tailored to suit your requirement.